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Imaging of solder and wire joints in flip-chip and wire bonded devices. In-situ studies of defect evolution

Computed laminography is combined with high-energy synchrotron radiation for three-dimensional imaging of strongly absorbing flat objects. High spatial resolution down to the micrometer scale can be attained, even for macroscopically large lateral size of devices. By use of white radiation, a temporal resolution between successive 3D images on the scale of some seconds allows rapid scanning of large specimen areas with considerable inspection throughput. Imaging of solder and wire joints in flip-chip and wire bonded devices and in-situ studies of defect evolution and repair demonstrates the application potential of the laminography method for 3D quality assurance in microsystem technology (see Figure 1.).

Unknown reliability is still the major limiting factor for the application of new microsystems and micromaterials. New materials and compounds come to use in products before their properties are completely investigated. High functionality leads to superposition of different loads. High-level
integration gives rise to interacting failure mechanisms. The resulting damage potential often limits massive use and security relevant applications. Often quality assurance requires the employment of non destructive testing techniques (NDT). Inspection of modern microsystem
devices suffer from hidden quality relevant elements which cannot be accessed by visual inspection methods. Therefore, high resolution 2D and
3D X-ray imaging methods such as digital radiography and computed tomography (CT) etc  have been applied for defect recognition in microsystem components and devices. Synchrotron Radiation Computed Tomography (SRCT) has extended the limits of laboratory CT in directionn of quantitative absorption tomography and high resolution microtomography. Improved resolution is usually achieved via miniaturization of the effective X-ray sensor pixel sizes. As a consequence, the field of view of the detector system reduces simultaneously. Conventional CT, however, has the constraint to keep the whole illuminated specimen volume during a full tomographic rotation within the detectors field of view. To meet the constraint requires for larger samples, before starting the measurements, to extract the regions of interest - usually by cutting a small cylinder out from the device. Such surgical interference, in fact, is becoming a serious drawback for a
method to be used for non-destructive inspection.

Figure 1: 3D real-time imaging by in-situ Synchrotron Radiation Computed Laminography (SRCL) of self repairing by thermal treatment during 10 minutes of a flip-chip test device. X-ray energy between 30 and 50 keV. 600 projections per laminographic scan recorded in 20 secs (30 frames per sec). The slices (a)-(f) through the reconstructed 3D data sets represent selected time steps after 0, 1, 2, 3, 4 and 10 min of heat treatment at 300°C.





Examination of state of the art silicon integrated circuit (IC) memory devices inside organic packages

This study focuses on commercially available ICs embedded inside standard organic packages. The best description of such packages is obtained by an examination under state of the art X-ray-radiography. Figure 2 shows images obtained with a Feinfocus system.

Figure 2






Figure 2: X-ray radiography of commercial memory ICs inside an organic package





Organic packages with multiple die, including cross section packages:
Additionally packages with 2 or more silicon die inside (from a variety of chip manufacturers) were examined. The stacking of silicon pieces is common practice in the semiconductor industry, and it is likely to increase in complexity over the next few years. Cross section of packages is a standard step in failure analysis of packaged ICs. The technique requires extreme care not to destroy the evidence during the cutting and/or polishing processes.

The aims of the performed measurements were:

  • To demonstrate for the first time the non invasive characterisation of the silicon lattice (i.e. examine defect/dislocation/stacking faults/etc) in commercially available state of the art packaged flash memory microchips produced by Intel Ireland. We have achieved the goal, demonstrating that white beam topography is a well suited nondestructive method to “view” the silicon lattice in organically packaged microphips. This is to our knowledge the first time that a package die has been examined by XRT.